Embodiments of the present invention relate to a semiconductor device, a method for operating the same, and a semiconductor system including the same, and more particularly, to a technology for reducing a data read time of a memory cell of a semiconductor device.
Generally, a memory device receives a write command or a read command from a host. Thereafter, a memory controller in the memory device operates to program data in or read out data from a corresponding cell in a memory cell region.
Memory devices are classified as volatile memory devices or non-volatile memory devices according to whether data is retained or not when a power source is cut off. Recently, electronic appliances have been developed to have lower power consumption and smaller sizes. Thus, non-volatile memory devices such as flash memory devices are widely used in various electronic appliances.
A flash memory device is a type of electrically erasable and programmable read-only memory (EEPROM) in which multiple memory regions can be erased or programmed by a single program action.
A system including a flash memory device can operate more quickly and more effectively than a system which reads data from and writes data in other memory devices. All types of flash memory devices include cells that wear out after a predetermined number of erase operations. This is because an insulation film enclosing a charge storage element of a cell, which is configured to store data, is damaged by the erase operations.
A flash memory device is designed to retain data stored therein even when it is not powered. That is, a flash memory device can retain stored data without power consumption.
In addition, a flash memory device has excellent resistance to physical impact and a very high read access speed. As a result, flash memory devices have been widely used as storage devices in mobile products using battery power.
A flash memory device is classified as a NOR flash memory device or a NAND flash memory device depending on the type of logic gate used in the storage unit of the device.
A flash memory device is configured to store data in an array of transistors called cells. Flash memory devices may include a single-level cell or a multi-level cell. In a single-level cell device, a cell stores 1-bit data. In a multi-level cell device, a cell stores two or more bit data by changing an amount of charges on a floating gate of the cell.
A memory cell region of a flash memory device includes a plurality of strings. Each string includes memory cells coupled in series to each other. Each string further includes selection transistors formed at both ends thereof. Memory cells disposed in different strings may be electrically coupled to each other through a word line.
In addition, individual strings are electrically coupled to a page buffer, which is configured to sense data, through a bit line. In order to record data in a selected memory cell, a program operation and a verification operation are repeatedly performed a predetermined number of times until data temporarily stored in the page buffer is programmed in the selected memory cell.
If a program voltage is applied to a control gate of the selected memory cell, a tunneling phenomenon occurs in a floating gate of the selected memory cell so that the program operation is carried out. In addition, if an erase voltage is applied to a bulk of the selected memory cell, the tunneling phenomenon occurs in the floating gate so that an erase operation is carried out. For reference, the program voltage is applied to the selected memory cell through a word line coupled to the control gate of the selected memory cell.